Give your users greater experience with higher memory in an ultra-low-power MCU
The high-speed memories in the STM32WBA62CIU6 wireless MCU from STMicroelectronics are up to 2MB dual bank flash memory with ECC and 512KB SRAM 100 Kcycles which are paired with a high-performance Arm® Cortex®-M33 RISC core with TrustZone® security.
To add design flexibility, the multiprotocol support enables the embedded 2.4GHz radio to implement Bluetooth® LE 6.0, IEEE 802.15.4, Matter, Zigbee and Thread, and includes concurrent operation modes. Up to eight antennas, and an external power amplifier, are supported, in addition to a packet traffic arbitration (PTA) interface.
The enhanced I/Os and peripherals are connected to the advanced high-performance bus (AHB) and to the advanced peripheral bus (APB) on the 32-bit multi-AHB matrix.
Certification is simplified as the STM32WBA62CIU6 is certified to platform security architecture (PSA) Level 3 and SESIP Level 3, in addition to complying to the radio equipment directive (RED) and US security standards.
The Cortex-M33 core offers a floating-point unit (FPU), to support all Arm single-precision data-processing instructions and data types, in addition to featuring a full set of digital signal processing (DSP) instructions and a memory protection unit (MPU) to boost application security.
Security on the STM32WBA62CIU6 is compliant with the Arm trusted-based security architecture (TBSA) and offers a secure boot, secure data storage, and secure firmware update. Secure firmware installation allows the OEM to secure code provisioning during production. Flexible life-cycle management is through multi-level readout protection and debug unlock with password.
Firmware hardware isolation is supported by securable peripherals, memories and I/Os, in addition to privilege configuration of peripherals and memories.
Protection for the embedded memory handles readout protection, write protection, secure, and hide protection areas. Dedicated peripherals provide security with a fast AES coprocessor, secure AES coprocessor with DPA resistance and a hardware unique key that can be shared by hardware with fast AES. There is also a public key accelerator (PKA) with DPA resistance, a HASH hardware accelerator, and a true random number generator.
Active tamper detection and protection against transient perturbation attacks is provided by internal monitoring which generates secret data erase in an attack. Hardware semaphores allow synchronization between software processes.
The radio, communication, analog, and timer peripherals can be functional and autonomous in Stop mode with direct memory access due to the background autonomous mode (BAM).