Launch of industry’s first terabit-scale secure Ethernet transceiver with port aggregation

Microchip has introduced a new family of META-DX2+ physical layer (PHY) devices in response to growing demand for 112G PAM4 network connectivity for enterprise Ethernet switching platforms, as well as cloud data center and telecom service provider switches and routers. 

META-DX2+ from Microchip enables OEMs to double router and switch system capacity with 112G PAM4 connectivity for 800G ports.

The META-DX2+ Ethernet transceivers are the industry’s first to integrate 1.6 Tbits/s of line-rate end-to-end encryption and port aggregation. This enables networking equipment OEMs to maintain a compact footprint in the transition to 112G PAM4 connectivity in enterprise Ethernet networking equipment. The move to 112G PAM4 is also backed by a Microchip META-DX retimer and PHY portfolio and the META-DX2L retimer. 

The configurable 1.6 Tbits/s datapath architecture of the META-DX2+ offers twice the performance of the next best competing devices in total gearbox capacity and hitless 2:1 protection switch mux modes, enabled by its unique ShiftIO capability. Flexible XpandIO port-aggregation capabilities optimize router/switch port utilization when supporting low-rate traffic.  

The new META-DX2+ devices also include IEEE 1588 Class C/D Precision Time Protocol support for the nanosecond-accurate timestamping required for 5G and enterprise business-critical services. 

By offering a portfolio of footprint-compatible retimers and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec functionality based on a common board design and software development kit.

Like the META-DX2L retimer, the new series of META-DX2+ PHYs can be used with Microchip‚Äôs PolarFire¬ģ FPGAs, the ZL30632 high-performance phase-locked loop, oscillators, voltage regulators, and other components which have been pre-validated as a system to help speed designs into production.

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